On- and Off-chip Signaling and Synchronization Methods in Electrical Interconnects

Abstract

Advances in integrated circuit (IC) fabrication technology, coupled with aggressive circuit design, have led to an exponential growth in speed and integration levels. However, to improve overall system performance, the communication speed between on-chip subsystems and between ICs in printed circuit board must increase accordingly. Currently, communication bus links in various applications approach Gbps (gigabits per second) data rates. These applications include high-speed network switching, local area network, memory buses, and multiprocessor interconnection networks. In this article, we analyze the most common (popular) CMOS implementations of high speed on- and off-chip links (electrical interconnects) and show that the links’ performance should continue to scale with technology. In addition, we point to the fact that global electrical interconnects are widely acknowledged as a limiting factor in future on-chip and off-chip designs. Novel electrical interconnect driving techniques like multi-level multi-wire signaling, and GALS synchronization method primarily intended to improve performance of on-chip electrical interconnects, has been shortly analyzed. In the future, in order to handle the electrical interconnects’ finite bandwidth (data rate higher than 100 Gbps), however, more sophisticated signaling and synchronization methods will be required.